Classic CMOS logic circuits include N-channel pull-down circuitry and P-channel pull-up circuitry connected between ground and positive DC power supply terminals or rails of an integrated circuit chip. An output terminal between the N-channel and P-channel circuitry supplies circuitry downstream of the logic gate with a bi-level output signal, typically a voltage substantially at one of the rail voltages. The pull-up circuitry and pull-down circuitry are driven in parallel by binary input signals supplied to the logic gate. Usually, the pull-up circuitry includes multiple P-channel field effect transistors (FETs), while the pull-down circuitry includes N-channel FETs. In response to the logic function of the logic circuit being satisfied, the pull-up circuitry is activated to supply the voltage at the positive power supply terminal to the output terminal. If the logic function is not satisfied, the pull-down circuitry is activated to supply the low, typically ground power supply voltage to the output terminal. To provide these connections, the P-channel pull-up and N-channel pull-down circuitry include numerous elements. Such an arrangement requires significant space on the integrated circuit chip and complex components necessary to form the pull-up and pull-down circuits.
Contention based logic gates were developed to overcome the problems associated with the classic pull-up and pull-down circuit approach. Pseudo-NMOS logic gates are one type of contention based logic gates. A typical pseudo-NMOS logic gate includes a single P-channel FET connected between the positive rail and an output terminal and pull-down circuitry connected between the output terminal and ground rail. The P-channel field effect transistor connected between the positive rail and the output terminal has a gate electrode that is usually connected to ground, so that the P-channel FET is always biased on to a certain extent. If the logic function (which determines the configuration of the N-channel pull-down circuitry) is satisfied, the pull-down circuitry has a high impedance between the output terminal and the grounded rail so that the voltage at the positive DC power supply rail is coupled through the P-channel FET to the output terminal, causing the output terminal to be at a high voltage. If the logic function is not satisfied, the pull-down circuitry provides a low impedance between the output terminal and the grounded rail. The low impedance of the pull-down circuitry is considerably lower than the turn on impedance of the P-channel FET so that the output terminal is at a voltage substantially less than one-half of the voltage between the power supply rails, i.e., the voltage at the output terminal is lower than a threshold associated with circuits driven by the pseudo-NMOS logic gate.
A problem with the traditional pseudo-NMOS logic gate is that the P-channel FET is always biased on and is drawing current from the positive power supply rail. The power dissipation has deleterious effects on the device, particularly with regard to heat.
Clocked pseudo-NMOS logic gates were developed to limit the current flowing through the P-channel transistor connected between the gate output terminal and positive power supply rail during one phase, i.e., portion, of each clock cycle. In a typical clocked pseudo-NMOS logic gate, each clock cycle is divided into two approximately equal duration phases or portions (i.e., each cycle includes two approximately equal half cycles) so that during a first clock cycle phase, the clock wave is at a positive voltage level, i.e., binary one level, and during a second phase the clock wave has a low voltage (i.e., approximately ground) or binary zero level. Such a clock wave is applied to the P-channel FET so current flows through the P-channel FET only during approximately fifty percent of each clock wave cycle. Hence, the percentage of time power is dissipated in the P-channel FET is reduced by approximately fifty percent.
However, for many applications the fifty percent duty cycle of the P-channel FET of the clocked pseudo-NMOS logic gate is excessively high. Simply reducing the on time of the P-channel FET to a lower than fifty percent duty cycle does not, in many instances, permit downstream circuitry driven by the clocked pseudo-NMOS logic gate to adequately detect the result of the output signal of the logic gate, i.e., to detect whether the logic function of the gate has been satisfied by the input signals thereof. This is particularly the case for high frequency circuits having clock frequencies in the one GigaHertz range.
It is, accordingly, an object of the present invention to provide a new and improved contention based logic gate.
Another object of the present invention is to provide a new and improved contention based logic gate having a duty cycle substantially less than fifty percent and wherein circuitry driven by the gate can be responsive to the gate output, even though the gate is driven at very high frequencies, for example, in the one GigaHertz range or higher.
Another object of the invention is to provide a new and improved pseudo-NMOS gate having low power dissipation as a result of low duty cycle operation, wherein the gate can be responsive to a large number of input signals.